?1 cxk5t81000atn/ayn -10llx/12llx pe96726-ps 131072-word 8-bit high speed cmos static ram description the cxk5t81000atn/ayn is a high speed cmos static ram organized as 131072-words by 8-bits. special feature are low power consumption and high speed. the cxk5t81000atn/ayn is a suitable ram for portable equipment with battery back up. features extended operating temperature range: ?5 to +85? wide supply voltage range operation: 2.7 to 3.6v fast access time: (access time) 3.0v operation -10llx 100ns (max.) -12llx 120ns (max.) 3.3v operation -10llx 85ns (max.) -12llx 100ns (max.) low standby current: 28 a (max.) low data retention current: 24 a (max.) low power data retention: 2.0v (min.) package 8mm 13.4mm 32 pin tsop package function 131072-word 8-bit static ram structure silicon gate cmos ic sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. v cc gnd ce1 ce2 row decoder buffer i/o buffer a10 a11 a9 a8 a13 a15 a16 a14 a12 a7 a6 a5 a4 a3 a0 oe we i/o gate column decoder memory matrix 1024 1024 a1 a2 i/o1 i/o8 buffer buffer block diagram preliminary cxk5t81000atn 32 pin tsop (plastic) cxk5t81000ayn 32 pin tsop (plastic)
?2 cxk5t81000atn/ayn address input data input output chip enable 1, 2 input write enable input output enable input power supply ground no connection symbol description supply voltage input voltage input and output voltage allowable power dissipation operating temperature storage temperature soldering temperature ?time v cc v in v i/o p d topr tstg tsolder ?.5 to +4.6 ?.5 * 1 to v cc + 0.5 ?.5 * 1 to v cc + 0.5 0.7 ?5 to +85 ?5 to +150 235 ?10 v v v w ? ? ? ?s item symbol rating unit absolute maximum ratings (ta = 25?, gnd = 0v) * 1 v in , v i/o = ?.0v min. for pulse width less than 50ns. pin description a0 to a16 i/o1 to i/o8 ce1, ce2 we oe v cc gnd nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 19 20 21 22 23 24 25 26 27 28 29 30 32 31 17 cxk5t81000atn (standard pinout) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 19 20 21 22 23 24 25 26 27 28 29 30 32 31 17 cxk5t81000ayn (mirror image pinout) a11 a9 a8 a13 we ce2 a15 v cc nc a16 a14 a12 a7 a6 a5 a4 oe a10 ce1 i/o8 i/o7 i/o6 i/o5 i/o4 gnd i/o3 i/o2 i/o1 a0 a1 a2 a3 oe a10 ce1 i/o8 i/o7 i/o6 i/o5 i/o4 gnd i/o3 i/o2 i/o1 a0 a1 a2 a3 a4 a5 a6 a7 a12 a14 a16 nc v cc a15 ce2 we a13 a8 a9 a11 pin configuration (top view) h l l l l h h h h l h h l not selected not selected output disable read write high z high z high z data out data in i sb1 , i sb2 i sb1 , i sb2 i cc1 , i cc2 , i cc3 i cc1 , i cc2 , i cc3 i cc1 , i cc2 , i cc3 ce1 ce2 oe we mode i/o pin v cc current truth table : h?or ? dc recommended operating conditions (ta = ?5 to +85?, gnd = 0v) * 2 v il = ?.0v min. for pulse width less than 50ns. supply voltage input high voltage input low voltage item symbol min. v cc = 2.7 to 3.6v v cc = 3.3v 0.3v typ. max. unit v cc v ih v il 2.7 2.4 ?.3 * 2 3.3 3.6 v cc + 0.3 0.4 min. typ. max. 3.0 2.2 ?.3 * 2 3.3 3.6 v cc + 0.3 0.6 v
?3 cxk5t81000atn/ayn input leakage current output leakage current operating power supply current i li i lo i cc1 v in = gnd to v cc ce1 = v ih or ce2 = v il or oe = v ih or we = v il v i/o = gnd to v cc ce1 = v il , ce2 = v ih v in = v ih or v il i out = 0ma 10llx 12llx ?5 to +85? ?5 to +70? +25? ? ? ?10 0.48 0.12 28 14 1.4 ? ma 1 25 * 2 25 +1 +1 3 35 * 3 35 ? ? ma ma ma item symbol min. typ. * 1 max. unit test conditions electrical characteristics dc characteristics (v cc = 2.7 to 3.6v, gnd = 0v, ta = ?5 to +85?) * 1 v cc = 3.3v, ta = 25? * 2 i cc2 = 30ma for 3.3v operation (v cc = 3.3v 0.3v) * 3 i cc2 = 40ma for 3.3v operation (v cc = 3.3v 0.3v) average operating current output high voltage output low voltage standby current i cc2 i cc3 i sb1 i sb2 v oh v ol min. cycle duty = 100% i out = 0ma cycle time 1 s duty = 100% i out = 0ma ce1 0.2v ce2 3 vcc ?0.2v v il 0.2v v ih 3 vcc ?0.2v ce1 = v ih or ce2 = v il i ol = 2.0ma 2.4 0.4 v v i oh = ?.0ma ce2 0.2v ce1 3 vcc ?0.2v or { ce2 3 vcc ?0.2v input capacitance i/o capacitance item symbol test conditions min. typ. max. unit c in c i/o 8 10 pf pf v in = 0v v i/o = 0v i/o capacitance (ta = 25?, f = 1mhz) note) this parameter is sampled and is not 100% tested.
?4 cxk5t81000atn/ayn ac characteristics ac test conditions (ta = ?5 to +85?) ttl c l test circuit input pulse high level input pulse low level input rise time input fall time input and output reference level -10llx output load conditions -12llx v ih = 2.4v v il = 0.4v t r = 5ns t f = 5ns 1.4v c l * 1 = 100pf, 1ttl c l * 1 = 100pf, 1ttl item v cc = 2.7 to 3.6v conditions v ih = 2.2v v il = 0.6v t r = 5ns t f = 5ns 1.4v c l * 1 = 30pf, 1ttl c l * 1 = 100pf, 1ttl v cc = 3.3v 0.3v * 1 c l includes scope and jig capacitances.
?5 cxk5t81000atn/ayn read cycle (we = ?? * 1 t hz1 , t hz2 and t ohz are defined as the time required for outputs to turn to high impedance state and are not referred to as output voltage levels. * 2 t whz is defined as the time required for outputs to turn to high impedance state and is not referred to as output voltage level. write cycle item symbol min. max. min. max. -10llx v cc = 2.7 to 3.6v v cc = 3.3v 0.3v -12llx unit t rc t aa t co1 t co2 t oe t oh t lz1 t lz2 t olz t hz1 * 1 t hz2 * 1 t ohz * 1 100 10 10 5 100 100 100 50 40 35 120 10 10 5 120 120 120 60 40 35 min. max. min. max. -10llx -12llx 85 10 10 5 85 85 85 40 35 30 100 10 10 5 100 100 100 50 40 35 read cycle time address access time chip enable access time (ce1) chip enable access time (ce2) output enable to output valid output hold from address change chip enable to output in low z (ce1, ce2) output enable to output in low z (oe) chip disable to output in high z (ce1, ce2) output disable to output in high z (oe) ns ns ns ns ns ns ns ns ns ns item symbol min. max. min. max. -10llx v cc = 2.7 to 3.6v v cc = 3.3v 0.3v -12llx unit t wc t aw t cw t dw t dh t wp t as t wr t wr1 t ow t whz * 2 100 80 80 40 0 70 0 0 0 5 40 120 100 100 50 0 70 0 0 0 5 40 min. max. min. max. -10llx -12llx 85 70 70 35 0 60 0 0 0 5 35 100 80 80 40 0 70 0 0 0 5 40 write cycle time address valid to end of write chip enable to end of write data to write time overlap data hold from write time write pulse width address setup time write recovery time (we) write recovery time (ce1, ce2) output active from end of write write to output in high z ns ns ns ns ns ns ns ns ns ns ns
?6 cxk5t81000atn/ayn ?read cycle (1) : ce1 = oe = v il , ce2 = v ih , we = v ih address t aa t rc t oh data out previous data valid data valid ?read cycle (2) : we = v ih address t aa t rc t lz2 t ohz t oe t olz ce1 oe data out high impedance data valid t co1 t hz t lz1 t hz1 t hz2 t co2 ce2 timing waveform
?7 cxk5t81000atn/ayn ?write cycle (1) : we control address t aw t wc t cw t dh t whz t dw ce1 we data out high impedance data valid t ow oe data in t wr t as t wp ( * 1 ) t cw ce2 ( * 2 )( * 2 ) ?write cycle (2) : ce1 control address oe t wc t aw data valid t as t cw t wr1 t wp t dw t dh high impedance ce1 we data out data in t cw ce2 ( * 3 )
?8 cxk5t81000atn/ayn ?write cycle (3) : ce2 control address oe t wc t aw data valid t cw t wr1 t wp t dw t dh high impedance ce1 we data out data in t as t cw ce2 ( * 3 ) * 1 write is executed when both ce1 and we are at low and ce2 is at high simultaneously. * 2 do not apply the data input voltage of the opposite phase to the output while i/o pin is in output condition. * 3 t wr1 is tested from either the rising edge of ce1 or the falling edge of ce2, whichever comes earlier, until the end of the write cycle.
?9 cxk5t81000atn/ayn * 1 ?5 to +85? ?5 to +70? +25? v cc = 2.0 to 3.6v * 1 chip disable to data retention mode data retention voltage data retention setup time recovery time v dr i ccdr1 i ccdr2 t cdrs t r 2.0 0 5 0.4 0.48 * 2 3.6 24 12 28 v ? ? ns ns item symbol test conditions min. typ. max. unit data retention characteristics (ta = ?5 to +85?) * 1 ce1 3 vcc ?0.2v, ce2 3 vcc ?0.2v (ce1 control) or ce2 0.2v (ce2 control) * 2 v cc = 3.3v, ta = 25? data retention current v cc = 3.0v * 1 data retention waveform ?low supply voltage data retention waveform (1) (ce1 contol) v cc v ih v dr ce1 gnd t cdrs data retention mode ce1 3 v cc ?0.2v ?low supply voltage data retention waveform (2) (ce2 contol) t r data retention mode t r t cdrs ce2 0.2v v cc 2.7v v il ce2 gnd v dr 2.7v
package outline unit: mm cxk5t81000atn ?10 cxk5t81000atn/ayn cxk5t81000ayn sony code eiaj code jedec code package structure package material lead treatment lead material package mass epoxy resin solder plating 42 alloy * 8.0 0.1 * 11.8 0.1 13.4 0.3 1.2 max 0.5 0?to 10 0.05 ?0.05 + 0.1 0.145 a 0.1 detail a 0.2g note: dimension * ?does not include mold protrusion. m 0.08 0.5 0.2 1 32 16 17 32pin tsop (plastic) tsop-32p-l02 tsop032-p-0813.4-c sony code eiaj code jedec code package structure package material lead treatment lead material package mass epoxy resin solder plating 42 alloy * 8.0 0.1 * 11.8 0.1 13.4 0.3 1.2 max 0.5 0?to 10 0.05 ?0.05 + 0.1 0.145 a 0.1 detail a 0.2g note: dimension * ?does not include mold protrusion. m 0.08 0.5 0.2 1 32 16 17 32pin tsop (plastic) tsop-32p-l02r tsop032-p-0813.4-d
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